Liquid crystal displays are frequently used to provide displays for mobile phones and other handheld electronic devices, laptop and desktop computers, video cameras, large screen televisions, as well as demanding applications such as avionic cockpit displays. A liquid crystal display can provide a small, rugged, lightweight, and power-efficient device that can realize a high image quality. Moreover, one type of liquid crystal display, the active matrix liquid crystal display, can provide a display with a high reaction speed and minimal residual images making it well suited for digital televisions.
In a liquid crystal active matrix display, light emitting display pixels are driven independently by selectively activating thin-film transistors associated with each display pixel. A schematic view of a conventional active matrix liquid crystal display structure 10 is shown in FIG. 1. The display structure 10 includes gate bus lines 12 and data bus lines 14 that are connected to a gate driver circuit 16 and a data driver circuit 18, respectively. Thin-film transistors 20 are formed at the intersection of each of the gate bus lines 12 and data bus lines 14 and are each operatively associated with a particular display pixel. In this structure, gate electrodes of the thin-film transistors 20 are connected to the gate bus lines 12, source electrodes are connected to the data bus lines 14, and drains are connected to pixel electrodes 22. Each pixel electrode is associated with a particular light emitting display pixel of the matrix. When a voltage is applied to the gate electrode of a thin-film transistor 20 through an associated gate bus line 12, thin-film transistor 20 is turned on to provide pixel electrode 22 with the input signal voltage from data driver circuit 18 through the data bus lines 14. As a result, the configuration of the liquid crystal changes to regulate the amount of light being emitted by the display pixel.
Thin-film transistors for active matrix liquid crystal displays typically include a semiconductor material, usually polycrystalline silicon or amorphous silicon. Transistors that are made from amorphous silicon are usually formed with a back channel etched structure or a channel passivated structure. A cross sectional view of a conventional back channel etched thin-film transistor 24 is shown in FIG. 2. Generally, the transistor 24 comprises a thin-film layered structure and is formed on a glass substrate 26 and includes a gate electrode 28, gate dielectric layer 30, amorphous silicon layer 32, source contact region 34, drain contact region 36, channel region 38, and a passivation layer 40. The source contact region 34 and the drain contact region 36 also typically include contact enhancement layers 42 and 44 respectively, which are discussed in more detail below.
Semiconductor devices, such as thin-film transistors, are typically designed and manufactured according to a predetermined set of design rules. Generally, a particular set of design rules specifies certain device parameters that device designers agree to follow in order to provide a standardized manufacturing process. For example, a typical set of design rules specifies parameters such as the smallest feature size allowed, the smallest feature spacing allowed, and the minimum overlap of features on different layers allowed, as well as many others. One factor used in determining such minimum design rules is defined by the minimum processable feature sizes for patterning technology such as photolithography.
One advantageous feature of a back channel etched structure is that it can provide a transistor with a relatively small channel length. By this method, structures can be created with a channel length that has the minimum feature size allowed in accordance with a predetermined set of design rules. Referring to FIG. 2, the channel length of the transistor 24 is indicated by reference numeral 46 and is at least partially defined by an edge of the contact enhancement layer 42 and the contact enhancement layer 44. A small channel length is desirable because a transistor with sufficient on-current can be formed in a relatively small device area. However, this type of structure can be difficult to fabricate. Generally, the contact material for the source and drain contact regions, 34 and 36, is deposited as a thin-film over a contact enhancement layer formed on a surface of the amorphous silicon layer and subsequently patterned and etched to define the source and drain contact regions, 34 and 36. This etching step requires precise control so that the contact enhancement layer is sufficiently removed to define the channel and so that the etching process does not excessively thin the amorphous silicon layer. Typically, this is done by starting with an amorphous silicon layer that is thicker than needed. However, an amorphous silicon layer that is thicker than actually required can adversely affect the device performance by causing enhanced photosensitivity and lower device on-current. Moreover, because such etching processes are generally more difficult to control than deposition processes, it can be difficult to form devices that meet performance specifications within sufficient tolerances.
Regarding a channel passivated structure, a cross sectional view of a conventional channel passivated thin-film transistor structure 48 is shown in FIG. 3. Like the back channel etched transistor 24, a typical transistor 48 comprises a thin-film layered structure and is formed on a glass substrate 50. The transistor 48 includes a gate electrode 52, gate dielectric layer 54, amorphous silicon layer 56, etch stop layer 58, source contact region 60, drain contact region 62, channel region 64, and a cap layer 66. The source contact region 60 and the drain contact region 62 also usually include contact enhancement layers 68 and 70 respectively, which are discussed in more detail below.
One advantage of this structure is that the thickness of the amorphous silicon layer 56 can be optimized for device performance unlike in the back channel etched structure. That is, in the channel passivated structure, the source and drain contact regions, 68 and 70, are defined by etching a region 72 and the etch stop layer 58 is used to protect the amorphous silicon layer 56 from being undesirably thinned when the region 72 is etched. In other words, the thickness of the amorphous silicon layer 56 is controlled purely by a controlled deposition process and is unchanged by the etching process. However, the minimum channel length for the channel passivated structure is necessarily larger than the channel length that can be obtained in the back channel etched structure. Specifically, the region 72 is the feature that can be designed to have the minimum device geometry dimension 74 as defined by the design rules. In this structure, the length of the etch stop layer 58 needs to be greater than the length of the region 72 in order to allow for photolithography registration tolerances. Accordingly, channel length 76 is defined by the length of the etch stop layer 58 and not as the distance between an edge of the contact enhancement layer 68 and the contact enhancement layer 70. The larger channel length of this type of device can result in a larger transistor size for a particular pixel drive current in a liquid crystal display and can also decrease the pixel aperture ratio and luminance.
Prior art back channel etched structures and the channel passivated structures use contact enhancement layers for the source and drain contact regions. Use of these contact enhancement layers can reduce the threshold voltage of the transistor from over 15 volts, without the contact enhancement layer, to less that 5 volts, with the contact enhancement layer. Moreover, the subthreshold voltage slope can also be increased and together with the reduced threshold voltage provides efficient charging of the liquid crystal display pixels.
Typically, the contact enhancement layers comprise highly doped n-type amorphous silicon formed by plasma enhanced chemical vapor deposition. In this process, silane gas is used to supply the silicon while phosphene is used to provide phosphorous as the n-type dopant. Both of these gases can be difficult to handle. In particular phosphene gas requires complex and expensive gas handling techniques and systems. Moreover, because a typical transistor includes both intrinsic amorphous silicon as well as doped amorphous silicon, separate deposition systems are required for each of these materials in order to protect against introducing the dopant species into the intrinsic amorphous silicon.